Memory devices are typically provided as internal, semiconductor, integrated circuits in computers or other electronic devices. There are many different types of memory including random-access memory (RAM), read only memory (ROM), dynamic random access memory (DRAM), synchronous dynamic random access memory (SDRAM), and flash memory.
A flash memory is a type of memory that can be erased and reprogrammed in blocks instead of one byte at a time. A typical flash memory comprises a memory array, which includes a large number of memory cells. Each of the memory cells includes a floating gate field-effect transistor capable of holding a charge. The cells are usually grouped into blocks. Each of the cells within a block can be electrically programmed in a random basis by charging the floating gate. The data in a cell is determined by the presence or absence of the charge in the floating gate. The charge can be removed from the floating gate by a block erase operation.
FIG. 1 illustrates a simplified diagram of one embodiment for a portion of a typical prior art NAND flash memory array. The memory array of FIG. 1, for purposes of clarity, does not show all of the elements typically required in a memory array. For example, only two bit lines are shown (BL1 and BL2) when the number of bit lines required actually depends upon the memory density. The bit lines are subsequently referred to as (BL1–BLN).
The array is comprised of an array of floating gate cells 101 arranged in series columns 104, 105. Each of the floating gate cells 101 are coupled drain to source in each series chain 104, 105. A word line (WL0–WL31) that spans across multiple series strings 104, 105 is coupled to the control gates of every floating gate cell in a row in order to control their operation. The bit lines (BL1–BLN) are eventually coupled to sense amplifiers (not shown) that detect the state of each cell.
In operation, the word lines (WL0–WL31) select the individual floating gate memory cells in the series chain 104, 105 to be written to or read from and operate the remaining floating gate memory cells in each series string 104, 105 in a pass through mode. Each series string 104, 105 of floating gate memory cells is coupled to a source line 106 by a source select gate 116, 117 and to an individual bit line (BL1–BLN) by a drain select gate 112, 113. The source select gates 116, 117 are controlled by a source select gate control line SG(S) 118 coupled to their control gates. The drain select gates 112, 113 are controlled by a drain select gate control line SG(D) 114.
During a typical prior art programming operation, the selected word line for the flash memory cell to be programmed is biased with a series of incrementing voltage programming pulses that start at an initial voltage that is greater than a predetermined programming voltage (e.g., approximately 16V). After each programming pulse, a verification operation with a word line voltage of 0V is performed to determine if the cell's threshold voltage Vt has increased to the properly programmed level (e.g., 0.5V).
The unselected word lines for the remaining cells are typically biased at a voltage that is less than the programming voltage (e.g., approximately 10V) during the program operation. In one embodiment, the unselected word line voltages can be any voltage above ground potential. Each of the memory cells is programmed in a substantially similar fashion.
One problem with the prior art flash memory array architecture is the large amount of current that is conducted by the source lines of the array. Typically, 2048 memory cells are on each word line and are read simultaneously when the word line is selected. A common source line has to conduct the current of all of these memory cells. This increases the noise experienced by the memory cells of the array.
Additionally, in order for the shared source line to carry such a large current, it must be made relatively large in comparison to other elements of the array. Therefore, even though most of the elements of the array can be scaled to increase the density of the memory device, the shared source line needs to remain relatively large to carry the large amounts of current during read and verify operations. The source line thus limits the scaling possible for a flash memory array.
For the reasons stated above, and for other reasons stated below which will become apparent to those skilled in the art upon reading and understanding the present specification, there is a need in the art for a memory array that generates less noise and can be more readily scaled.